C. Luk, J. Buan, T. Ohshida, P.J. Wang, Y. Oryu, C.C. Huang and N. Jarvis, “Hacking skew measurement,” DesignCon 2018, 01/30 – 02/01/2018, Santa Clara, CA.
J. Moreira, C.C. Huang and D. Lee, “DUT ATE test fixture S-parameters estimation using 1x-reflect methodology,” BiTS China Workshop, 09/07/2017, Shanghai, China.
J. Balachandran, K. Cai, Y. Sun, R. Shi, G. Zhang, C.C. Huang and B. Sen, “Aristotle: A fully automated SI platform for PCB material characterization,” DesignCon 2017, 01/31-02/02/2017, Santa Clara, CA.
C.C. Huang, “In-Situ De-embedding,” EDI CON, Beijing, China, 04/19 to 04/21/2016.
C. Luk, J. Buan, A. Nagao, T. Takada and C.C. Huang, “Tradeoffs between tightly and loosely coupled differential vias for multi-Gbps design,” DesignCon 2016, 01/19-01/22/2016, Santa Clara, CA.
K. Aihara, J. Buan, A. Nagao, T. Takada and C.C. Huang, “A novel method to reduce differential crosstalk in a high-speed channel,” DesignCon 2015, 01/27-01/30/2015, Santa Clara, CA.
K. Aihara, J. Buan, A. Nagao, T. Takada and C.C. Huang, “Minimizing differential crosstalk of vias for high-speed data transmission,” EPEPS 2014, 10/26-10/29/2014, Portland, OR.
A. Nagao, T. Takada, C.C. Huang, J. Buan, K. Aihara, P. Li and A. Mihara, “New methodologies for 25+ Gbps connector characterization,” DesignCon 2014, 01/28-01/31/2014, Santa Clara, CA.
J. Buan, T. Takada, F. Cheng, J. Weng, C. Luk, T. Arai, C.C. Huang, D. Yanagawa, P. Li, Y. Yang, “Embedded DC blocking capacitors in connectors – study of impacts on PCB design and high speed serial link performance,” DesignCon 2012, 01/30-02/02/2012, Santa Clara, CA.